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ds05-30339-1e fujitsu semiconductor data sheet memory dram card jeida * [dram card guide line ver. 2.0] conformable MB98B7515/7516/7517/7518 dynamic random access memory card 16 m/32 m - byte n description the MB98B7515 is a dram card (4,194,304 words 32 bits) with eight mb8117400as mounted. the mb98b7516 is a dram card (4,194,304 words 36 bits) with eight mb8117400as and four mb814100a mounted. the mb98b7517 is a dram card (8,388,608 words 32 bits) with sixteen mb8117400a's mounted. the mb98b7518 is a dram card (8,388,608 words 36 bits) with sixteen mb8117400a's and eight mb814100a mounted. the connector used for these series is a 88-pin, two-piece connector. this card complies with jeida [dram card guide line ver. 2.0] *: japanese electronic industry development association (jeida). n features outside dimensions: 85.6 mm 54.0 mm 3.3 mm supply voltage: +5 v 5 % input/output level ttl compatible 2,048 refresh cycles / 128 ms (dispersion refresh) cas before ras refresh, ras only refresh, and hidden refresh are possible. high-speed page mode is available. dram with substrate bias generator is mounted. 88-pin two-piece connector n package 88-pin dram card (crd-88p-m01)
2 MB98B7515/7516/7517/7518 n product class part number memory device memory configuration access time (max.) ns cycle time (min.) ns power dissipation (max.) mw normal mode high-speed page mode normal mode high-speed page mode oper- ating stand-by ttl cmos MB98B7515-70 mb8117400 a-60 8 pcs 4 m 32 70 45 130 50 4,988 137 47.3 mb98b7516-70 mb8117400 a-60 8 pcs mb814100 a-60l 4 pcs 4 m 36 7,298 168 52.5 mb98b7517-70 mb8117400 a-60 16 pcs 8 m 32 5,093 221 89.3 mb98b7518-70 mb8117400 a-60 16 pcs mb814100 a-60l 8 pcs 8 m 36 7,455 284 99.8 MB98B7515-80 mb8117400 a-70 8 pcs 4 m 32 80 50 150 55 4,305 137 47.3 mb98b7516-80 mb8117400 a-70 8 pcs mb814100 a-70l 4 pcs 4 m 36 6,405 168 52.5 mb98b7517-80 mb8117400 a-70 16 pcs 8 m 32 4,410 221 89.3 mb98b7518-80 mb8117400 a-70 16 pcs mb814100 a-70l 8 pcs 8 m 36 6,563 284 99.8
3 MB98B7515/7516/7517/7518 n pin assignments *1: the descriptions of ras pin/dq pin depend on the series. refer to n differences among the series for details. *2: the description of pd pin depends on the series. refer to n about pd pin for details. pin no pin symbol pin no pin symbol pin no pin symbol pin no pin symbol 1 gnd 23 cas 0 45 gnd 67 gnd 2dq 0 24 cas 1 46 dq 18 68 cas 3 3dq 1 25 n.c. 47 dq 19 69 ras 3 * 1 4dq 2 26 ras 2 48 dq 20 70 we 5dq 3 27 v cc 49 dq 21 71 pd 1 * 2 6dq 4 28 pd 2 * 2 50 dq 22 72 pd 3 * 2 7dq 5 29 pd 4 * 2 51 dq 23 73 gnd 8dq 6 30 pd 6 * 2 52 dq 24 74 pd 5 * 2 9v cc 31 n.c. 53 dq 25 75 pd 7 * 2 10 dq 7 32 n.c. 54 dq 26 * 1 76 pd 8 * 2 11 n.c. 33 dq 17 * 1 55 n.c. 77 n.c. 12 dq 8 * 1 34 dq 9 56 gnd 78 n.c. 13 a 0 35 n.c. 57 a 1 79 dq 35 * 1 14 a 2 36 dq 10 58 a 3 80 dq 27 15 v cc 37 v cc 59 a 5 81 dq 28 16 a 4 38 dq 11 60 a 7 82 dq 29 17 n.c. 39 dq 12 61 a 9 83 dq 30 18 a 6 40 dq 13 62 n.c 84 dq 31 19 a 8 41 dq 14 63 gnd 85 dq 32 20 a 10 42 dq 15 64 n.c. 86 dq 33 21 n.c. 43 dq 16 65 ras 1 * 1 87 dq 34 22 ras 0 44 gnd 66 cas 2 88 gnd (connector side) pin symbol pin name a0 to a 10 address ras 0 to ras 3 load address strobe cas 0 to cas 3 column address strobe we write enable dq 0 to dq 35 input/output data pd 1 to pd 8 presence detect pin n.c. no connection v cc power supply (+ 5 v) gnd ground (crd-88p-m01) 44 88 1 45
4 MB98B7515/7516/7517/7518 n block diagram ras 1 * ras 0 cas 0 ras 3 * ras 2 cas 2 d 0 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 8 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 1 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 9 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras m 0 * cas ras d in /d out m 4 * cas ras d in /d out dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 * d 2 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 10 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 3 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 11 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras m 1 * cas ras d in /d out m 5 * cas ras d in /d out dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 * cas 1 d 4 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 12 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 5 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 13 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras m 2 * cas ras d in /d out m 6 * cas ras d in /d out dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 * d 6 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 14 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 7 i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras d 15 * i/o 1 i/o 2 i/o 3 i/o 4 oe cas ras m 3 * cas ras d in /d out m 7 * cas ras d in /d out dq 27 dq 28 dq 29 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 * cas 3 u 0 to 2 cas 0 to cas 3 a 0 to a 10 we v cc gnd d 0 to d 15 , m 0 to m 7 d 0 to d 15 , m 0 to m 7 , u 1 to u 3 * : the descriptions of ras pin/dq pin and the class and number of the mounted device depend on the series. refer to n differences among the series for details. d 0 to d 15 mb8117400a m 0 to m 7 mb814100a u 0 to u 2 74act11244
5 MB98B7515/7516/7517/7518 n differences among the series 1. list of pins and mounted devices : mounted ?: not mounted MB98B7515 mb98b7516 mb98b7517 ras 0 ras 1 ras 2 ras 3 dq 0 to dq 7 dq 8 dq 9 to dq 16 dq 17 dq 18 to dq 25 dq 26 dq 27 to dq 34 dq 35 d 0 to d 1 d 8 to d 15 m 0 to m 3 m 4 to m 7 mb98b7518 pin device part number series
6 MB98B7515/7516/7517/7518 n functional truth table 1. read/write modes 2. ras only refresh mode 3. cas before ras refresh mode ras 0 ras 1 ras 2 ras 3 cas 0, 1 cas 2, 3 active memory dq 0 to dq 17 dq 18 to dq 35 hhhhhh high-z high-z lhhhlhd 0 to d 3 , m 0, 1 i/o data high-z hlhhlhd 8 to d 11 , m 4, 5 i/o data high-z hhlhhld 4 to d 7 , m 2, 3 high-z i/o data hhhlhld 12 to d 15 , m 6, 7 high-z i/o data lhlhlld 0 to d 7 , m 0 to m 3 i/o data l lxxxx prohibited operation hlhllld 0 to d 7 , m 0 to m 3 i/o data x x l l x x prohibited operation ras 0 ras 1 ras 2 ras 3 cas 0, 1 cas 2, 3 active memory dq 0 to dq 17 dq 18 to dq 35 lhhhhhd 0 to d 3 , m 0 , 1 high-z hlhhhhd 8 to d 11 , m 4 , 5 high-z hhlhhhd 4 to d 7 , m 2 , 3 high-z hhhlhhd 12 to d 15 , m 6 , 7 high-z lhlhhhd 0 to d 7 , m 0 to m 3 high-z l lxxxx prohibited operation hlhlhhd 8 to d 15 , m 4 to m 7 high-z x x l l x x prohibited operation ras 0 ras 1 ras 2 ras 3 cas 0, 1 cas 2, 3 active memory dq 0 to dq 17 dq 18 to dq 35 lhhhlhd 0 to d 3 , m 0 , 1 high-z hlhhlhd 8 to d 11 , m 4 , 5 high-z hhlhhld 4 to d 7 , m 2 , 3 high-z hhhlhld 12 to d 15 , m 6 , 7 high-z lhlhlld 0 to d 7 , m 0 to m 3 high-z l lxxxx prohibited operation hlhllld 8 to d 15 , m 4 to m 7 high-z x x l l x x prohibited operation
7 MB98B7515/7516/7517/7518 4. hidden refresh mode x: ? or ?? n absolute maximum ratings (see warning) (voltage is with reference to the gnd (ground)) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (voltage is with reference to the gnd (ground)) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. ras 0 ras 1 ras 2 ras 3 cas 0, 1 cas 2, 3 active memory dq 0 to dq 17 dq 18 to dq 35 h ? lhhhlhd 0 to d 3 , m 0 , 1 i/o data high-z hh ? lhhlhd 8 to d 11 , m 4 , 5 i/o data high-z hhh ? lh h ld 4 to d 7 , m 2 , 3 high-z i/o data hhhh ? lh ld 12 to d 15 , m 6 , 7 high-z i/o data h ? lhh ? lh l ld 0 to d 7 , m 0 to m 3 i/o data h ? lh ? lxxxx prohibited operation hh ? lhh ? ll ld 8 to d 15 , m 4 to m 7 i/o data xxh ? lh ? l x x prohibited operation parameter symbol value unit MB98B7515 mb98b7516 mb98b7517 mb98b7518 supply voltage v cc ?.5 to +6.0 v input voltage v in 0 to v cc v output voltage v out 0 to v cc v storage temperature t stg ?0 to +70 c power dissipation p d 8 121624w output current (d.c.) l out 50 ma parameter symbol min. typ. max. unit ambient operating temperature supply voltage v cc 4.75 5.0 5.25 v 0 c to +55 c v ss 000 ?igh level input voltage (all input pins) v ih 2.4 v cc v ?ow level input voltage (all input pins) v il 0 0.8 v
8 MB98B7515/7516/7517/7518 n electrical characteristics 1. dc characteristics (1) MB98B7515 note 3 (on the recommended operating conditions) parameter notes symbol min. max. unit measuring conditions supply current (when normally operating) *2 i cc1 660 ma average supply current t rc = min. ras , cas cycling supply current (when stand-by) ttl i cc2 ?0 ma ras = cas = v ih cmos 9 ras = cas v cc ?.2 v supply current (on ras only refresh) *2 i cc3 660 ma average supply current t rc = min. ras cycling, cas = v ih supply current (in high- speed page mode) *2 i cc4 660 ma average supply current t pc = min. ras = v il , cas cycling supply current (on cas before ras refresh) *2 i cc5 660 ma average supply current t rc = min. ras cycling, cas before ras input leakage current cas 0 to cas 3 a 0 to a 10 , we i i(l) ?0 10 m a (0 v v in 5.25 v) (0 v except the measured pin, 4.75 v v cc 5.25 v) ras 0 , ras 2 ?0 30 output leakage current dq 0 to dq 7 , dq 9 to dq 16 dq 18 to dq 25 , dq 27 to dq 34 i o(l) ?0 10 m a (with output impedance high 0 v v out 5.25 v) ?igh level output voltage *1 v oh 2.4 v (i oh = ? ma) ?ow level output voltage *1 v ol 0.4 v (i ol = 4.2 ma) 3
9 MB98B7515/7516/7517/7518 (2) mb98b7516 note 3 (on the recommended operating conditions) parameter notes symbol min. max. unit measuring conditions supply current (when normally operating) *2 i cc1 1060 ma average supply current t rc = min. ras , cas cycling supply current (when stand-by) ttl i cc2 ?5 ma ras = cas = v ih cmos 10 ras = cas v cc ?.2 v supply current (on ras only refresh) *2 i cc3 1060 ma average supply current t rc = min. ras cycling, cas = v ih supply current (in high- speed page mode) *2 i cc4 860 ma average supply current t pc = min. ras = v il , cas cycling supply current (on cas before ras refresh) *2 i cc5 980 ma average supply current t rc = min. ras cycling, cas before ras input leakage current cas 0 to cas 3 a 0 to a 10 , we i i(l) ?0 10 m a (0 v v in 5.25 v) (0 v except the measured pin, 4.75 v v cc 5.25 v) ras 0 , ras 2 ?0 40 output leakage current dq 0 to dq 7 , dq 9 to dq 16 dq 18 to dq 25 , dq 27 to dq 34 i o(l) ?0 10 m a (with output impedance high 0 v v out 5.25 v) dq 8 , dq 17 , dq 26 , dq 35 ?0 20 ?igh level output voltage *1 v oh 2.4 v (i oh = ? ma) ?ow level output voltage *1 v ol 0.4 v (i ol = 4.2 ma) 3
10 MB98B7515/7516/7517/7518 (3) mb98b7517 notes 3, 19 (on the recommended operating conditions) parameter notes symbol min. max. unit measuring conditions supply current (when normally operating) *2 i cc1 680 ma average supply current t rc = min. ras , cas cycling supply current (when stand-by) ttl i cc2 ?5 ma ras = cas = v ih cmos 17 ras = cas v cc ?.2 v supply current (on ras only refresh) *2 i cc3 680 ma average supply current t rc = min. ras cycling, cas = v ih supply current (in high- speed page mode) *2 i cc4 680 ma average supply current t pc = min. ras = v il , cas cycling supply current (on cas before ras refresh) *2 i cc5 680 ma average supply current t rc = min. ras cycling, cas before ras input leakage current cas 0 to cas 3 a 0 to a 10 , we i i(l) ?0 10 m a (0 v v in 5.25 v) (0 v except the measured pin, 4.75 v v cc 5.25 v) ras 0 to ras 3 ?0 30 output leakage current dq 0 to dq 7 , dq 9 to dq 16 dq 18 to dq 25 , dq 27 to dq 34 i o(l) ?0 20 m a (with output impedance high 0 v v out 5.25 v) ?igh level output voltage *1 v oh 2.4 v (i oh = ? ma) ?ow level output voltage *1 v ol 0.4 v (i ol = 4.2 ma) 3
11 MB98B7515/7516/7517/7518 (4) mb98b7518 notes 3, 19 (on the recommended operating conditions) parameter notes symbol min. max. unit measuring conditions supply current (when normally operating) *2 i cc1 1080 ma average supply current t rc = min. ras , cas cycling supply current (when stand-by) ttl i cc2 ?5 ma ras = cas = v ih cmos 19 ras = cas v cc ?.2 v supply current (on ras only refresh) *2 i cc3 1080 ma average supply current t rc = min. ras cycling, cas = v ih supply current (in high- speed page mode) *2 i cc4 880 ma average supply current t pc = min. ras = v il , cas cycling supply current (on cas before ras refresh) *2 i cc5 1000 ma average supply current t rc = min. ras cycling, cas before ras input leakage current cas 0 to cas 3 a 0 to a 10 , we i i(l) ?0 10 m a (0 v v in 5.25 v) (0 v except the measured pin, 4.75 v v cc 5.25 v) ras 0 to ras 3 ?0 40 output leakage current dq 0 to dq 7 , dq 9 to dq 16 dq 18 to dq 25 , dq 27 to dq 34 i o(l) ?0 20 m a (with output impedance high 0 v v out 5.25 v) dq 8 , dq 17 , dq 26 , dq 35 ?0 30 ?igh level output voltage *1 v oh 2.4 v (i oh = ? ma) ?ow level output voltage *1 v ol 0.4 v (i ol = 4.2 ma) 3
12 MB98B7515/7516/7517/7518 2. ac characteristics notes 3, 4, 5 (1) MB98B7515/6/7/8-70 (on the recommended operating conditions) (continued) no. parameter notes symbol min. max. unit 1 refresh interval t ref 128 ms 2 random read/write cycle time t rc 130 ns 3 access time from ras *6,9 t rac ?0ns 4 access time from cas *7,9 t cac ?5ns 5 column address access time *8,9 t aa ?0ns 6 output data hold time t oh 2ns 7 output turn on delay time t on 2ns 8 output turn off delay time *10 t off ?5ns 9 turn on/turn off periods t t 550ns 10 ras precharge time t rp 50 ns 11 ras pulse width t ras 70 100000 ns 12 ras hold time t rsh 25 ns 13 ras cas precharge time t crp 15 ns 14 ras cas delay time *11,12 t rcd 20 45 ns 15 cas pulse width t cas 25 ns 16 cas hold time t csh 70 ns 17 cas precharge time *17 t cpn 10 ns 18 low address setup time t asr 10 ns 19 low address hold time t rah 10 ns 20 column address setup time t asc 2ns 21 column address hold time t cah 15 ns 22 ras column address delay time *13 t rad 15 30 ns 23 column address ras read time t ral 40 ns 24 column address cas read time t cal 40 ns 25 read instruction setup time t rcs 0ns 26 read instruction hold time from ras *14 t rrh 0ns 27 read instruction hold time *14 t rch 0ns 28 write instruction setup time *15 t wcs 2ns 29 write instruction hold time t wch 15 ns 30 write instruction pulse width t wp 15 ns
13 MB98B7515/7516/7517/7518 (continued) no. parameter notes symbol min. max. unit 31 write instruction ras read time t rwl 25 ns 32 write instruction cas read time t cwl 25 ns 33 data input setup time t ds 0ns 34 data input hold time t dh 25 ns 35 cas active display from ras precharge t rpc 5ns 36 ras cas setup time (cas before ras ) t csr 10 ns 37 ras cas hold time (cas before ras ) t chr 10 ns 38 we setup time from ras *18 t wsr 10 ns 39 we hold time from ras *18 t whr 10 ns 40 data input cas delay time t dzc 0ns 41 high-speed page mode read/write cycle time t pc 50 ns 42 access time from high-speed page mode cas precharge *9,16 t cpa ?5ns 43 high-speed page mode cas precharge time t cp 10 ns 44 ras hold time from high-speed page mode cas precharge t rhcp 40 ns
14 MB98B7515/7516/7517/7518 (2) MB98B7515/6/7/8-80 (on the recommended operating conditions) (continued) no. parameter notes symbol min. max. unit 1 refresh interval t ref 128 ms 2 random read/write cycle time t rc 150 ns 3 access time from ras *6,9 t rac ?0ns 4 access time from cas *7,9 t cac ?0ns 5 column address access time *8,9 t aa ?5ns 6 output data hold time t oh 2ns 7 output turn on delay time t on 2ns 8 output turn off delay time *10 t off ?0ns 9 turn on/turn off periods t t 550ns 10 ras precharge time t rp 60 ns 11 ras pulse width t ras 80 100000 ns 12 ras hold time t rsh 30 ns 13 ras cas precharge time t crp 15 ns 14 ras cas delay time *11,12 t rcd 20 50 ns 15 cas pulse width t cas 30 ns 16 cas hold time t csh 80 ns 17 cas precharge time *17 t cpn 10 ns 18 low address setup time t asr 10 ns 19 low address hold time t rah 10 ns 20 column address setup time t asc 2ns 21 column address hold time t cah 15 ns 22 ras column address delay time *13 t rad 15 35 ns 23 column address ras read time t ral 45 ns 24 column address cas read time t cal 45 ns 25 read instruction setup time t rcs 0ns 26 read instruction hold time from ras *14 t rrh 0ns 27 read instruction hold time *14 t rch 0ns 28 write instruction setup time *15 t wcs 2ns 29 write instruction hold time t wch 15 ns 30 write instruction pulse width t wp 15 ns
15 MB98B7515/7516/7517/7518 (continued) no. parameter notes symbol min. max. unit 31 write instruction ras read time t rwl 30 ns 32 write instruction cas read time t cwl 30 ns 33 data input setup time t ds 0ns 34 data input hold time t dh 25 ns 35 cas active display from ras precharge t rpc 5ns 36 ras cas setup time (cas before ras ) t csr 10 ns 37 ras cas hold time (cas before ras ) t chr 12 ns 38 we setup time from ras *18 t wsr 10 ns 39 we hold time from ras *18 t whr 10 ns 40 data input cas delay time t dzc 0ns 41 high-speed page mode read/write cycle time t pc 55 ns 42 access time from high-speed page mode cas precharge *9,16 t cpa ?0ns 43 high-speed page mode cas precharge time t cp 10 ns 44 ras hold time from high-speed page mode cas precharge t rhcp 50 ns
16 MB98B7515/7516/7517/7518 notes: *1. voltage reference is v ss . *2. output pin is open. supply current depends on cycle time and output load. if v il > ?.5 v, ras = v il and cas = v ih , supply current depends on the number of address changes. if ras = v il and cas = v ih , the value of either i cc1 , i cc3 , i cc4 or i cc5 indicates that the address change has occurred only one time. *3. a time delay of 200 m s (called the pause time) plus the dummy cycles (shown below) is necessary for these elements to function after power on. the dummy cycles are one of the following: eight ras only refresh cycles, or eight cas before ras refresh cycles (we = ??. if using the internal refresh counter, equal to or more than eight cas before ras refresh cycles must be used for the dummy cycles. *4. ac characteristics must be measured by using t t = 5 ns. *5. input reference levels for specifying the timing are the v ih (min.) and v il (max.).the transition time (t t ) is the time for a output voltage to switch from v ih tov il . *6. the t rac (max.) is guaranteed on the condition that t rcd t rcd (max.) and t rad t rad (max.). therefore, if t rcd > t rcd (max.) and t rad > t rad (max.), t rac will appear after the delay time equivalent to the difference between t rcd and t rcd (max.) or t rad and t rad (max.). *7. if t asc t aa - t cac - (t t ) with t rcd t rcd (max.) and t rad t rad (max.), the access time is dependent of the cas . *8. if t asc t aa - t cac - (t t ) with t rad t rad (max.), the access time is dependent of the column address. *9. 2ttl + 100pf load. *10. the t off is de?ed while the internal output buffer is in high impedance. *11. the t rcd (max.) is not a critical operating point, but a max. t rcd value that guarantees t rac (max.). in case t rcd > t rcd (max.), the access time depends on the t cac or t aa . *12. the t rcd (min.) = t rah (min.) + 2t t + t asc (min.). *13. the t rad (max.) is not a critical operating point, but a max.t rad value that guarantees t rac (max.). in case t rad >t rcd (max.), the access time depends on the t cac or t aa . *14. operation is guaranteed if one of the t rch or t rrh is met. *15. if t wcs t wcs (min.), the dq(output) pin shows open (high impedance) during this cycle. *16. the t cpa regulates the access time if the cas releases the column address latch, and this release consequently permits a new column address to be selected. therefore, the t cpa gets longer than t cpa (max.) if the t cp is long. *17. only cas before ras refresh cycle is de?ed. *18. the test mode is de?ed. *19. on reading, the bank 1 (controlled by ras 0 and ras 2 )and bank 2 (controlled by ras 1 and ras 3 ) must not work at the same time because the dq pin is common to both the bank 1 and bank 2 (the other must be in stand-by). 3. capacity between pins parameter symbol series min. max. units input capacity (a 0 to a 9 , we , cas 0 to cas 3 )c in1 common to series 20 pf input capacity (ras 0 to ras 3 )c in2 MB98B7515,7517 45 pf mb98b7516,7518 55 pf input/output capacity (dq 0 to dq 7 , dq 9 to dq 16 , dq 18 to dq 25 , dq 27 to dq 34 ) c dq1 MB98B7515,7517 30 pf mb98b7516,7518 35 pf input/output capacity (dq 8 , dq 17 , dq 26 , dq 35 )c dq2 mb98b7516 30 pf mb98b7518 35 pf 3 3 3 3 3
17 MB98B7515/7516/7517/7518 n timing diagram 1. read cycle cas we ras t rc t ras t rp t crp t asr t rah t csh t cas t rcd t rsh t rad t asc t cah t cal t ral t rrh t rch t rcs t dzc t rac t on t cac t aa t off t oh low address column address stable output period : ? or ? high-z add d in d out high-z
18 MB98B7515/7516/7517/7518 2. write cycle cas we ras : ? or ? add d in d out t rc t ras t rp t crp t csh t cas t rcd t rsh t asr t rah t rad t asc t cah t ral t cal t cwl t rwl t wcs t wch t ds t dh t wp stable input period high-z low address column address
19 MB98B7515/7516/7517/7518 3. high-speed page mode read cycle cas we ras : ? or ? add d in d out : stable output period t ras t rp t crp t rcd t rsh t asr t rah t asc t rad t cah t cas t rcs t rch t dzc t rac t off t oh t cac t on t aa t cpa t rch t rrh t cal t ral t pc t cp t csh t rhcp high ?z column address low address column address column address high-z
20 MB98B7515/7516/7517/7518 4. high-speed page mode write cycle cas we ras : ? or ? add d in d out t ras t rp t crp t rcd t rsh t asr t rah t asc t cah t cas t cal t pc t csh t rhcp t ral t rad t ds t dh t wp t wcs t wch stable input period stable input period stable input period t cwl t rwl column address low address column address column address high-z t cp
21 MB98B7515/7516/7517/7518 5. ras only refresh cycle 6. cas before ras refresh cycle cas ras : ? or ? add d out note: we is ? or ?? t ras t rc t asr t rah t rp t rpc t oh t off t crp low address high-z cas ras : ? or ? d out note: add is ? or ?? we t ras t rp t rpc t rc t oh t off t cpn t csr t chr t wsr t whr high-z
22 MB98B7515/7516/7517/7518 7. hidden refresh cycle cas we ras : ? or ? add d in d out stable output period t ras t rc t rp t rcd t rsh t asr t rah t asc t cah t rad t cpr t ral t chr t rcs t rac t off t oh t cac t on t aa t rrh t whr t wsr t dzc high-z high-z column address low address
23 MB98B7515/7516/7517/7518 n pd pin 1. list of pins 2. functional table * : refer to the ?ram card guide line ver 2.0 by the jeida for details of pd pins. pd 2 pd 3 pd 4 pd 5 pd 6 pd 7 pd 8 MB98B7515-70 gnd gnd n.c. gnd n.c. gnd n.c. n.c. mb98b7516-70 mb98b7517-70 gnd mb98b7518-70 MB98B7515-80 n.c. n.c. gnd mb98b7516-80 mb98b7517-80 gnd mb98b7518-80 mb98b7516 mb98b7517 mb98b7518 device class data 4 m 4 4 m 4 4 m 4 4 m 4 pd 1 pd 2 pd 3 pd 4 parity 4 m 1? m 1 address (quantity) data 11/11 low/column parity 11/11 low/column number of banks 1 2 pd 5 access time 70/80 ns pd 6 pd 7 refresh slow refresh pd 8 pd 1 MB98B7515 pd pin part number part number parameters
24 MB98B7515/7516/7517/7518 n label indication (for reference) the label indication is as follows by the jeida speci?ations: 1. label speci?ations 2. label format * : refer to the ?ram card guide line ver 2.0 by the jeida for details label speci?ations. n device handling precautions this device in composed of ?e electronic parts, so take care in handling or keeping it as below. the card is made ?e, so do not keep it in the high temperature nor high humidity, place line in the direct sun- shine nor near the heater. the card should not be bent, scratched, dropped nor be shocked violently. this device should never be taken a part. it could destroy the card or your personal computer hardware. to help you handle this device safely, request us the device speci?ations when purchasing this device. no. parameter MB98B7515 mb98b7516 mb98b7517 mb98b7518 1 connector type type a (5 v, 3.3 v) 2 address area 4 m words 8 m words 3 bit width 32 bits 36 bits 32 bits 36 bits 4 circuit con?uration ras/cas = 2/4 ras/cas = 4/4 5 address composition row/col = 11/11 6 access time t rac = 80 ns 7 refresh type slow refresh 8 operation mode high-speed page mode 9 supply voltage v cc = 5 v 10 expansion pd pin not applicable MB98B7515 mb98b7516 mb98b7517 mb98b7518 016m32r2c4a0 ?08 f0 p 5 016m36r2c4a0 ?08 f0 p 5 032m32r4c4a0 ?08 f0 p 5 032m36r4c4a0 ?08 f0 p 5 (1) (2) (3) (4) (5) (6) (7) (9) (8) (10) *: * is blank.
25 MB98B7515/7516/7517/7518 n package dimensions 88-pin dram card (crd-88p-m01) c 1994 fujitsu limited k88001sc-3-2 "a" (1.713.004) 43.500.10 (.061.002) details of "a" part 2.126 ?.002 +.004 ?0.05 +0.10 54.00 ref 1.550.05 1.000.05 1.000.05 (.039.002) (.039.002) 1.550.05 (.061.002) 85.600.20 (3.370.008) 10.50 (.413) 10.50 (.413) 3.300.10 (.130.004) 2?r1.00(.039) 3.300.20 (.130.008) 0.500.10(.020.004) typ. typ. 1.000.10(.039.004) 1.270.10 (.050.004) 1pin (2.126.004) 54.000.10 43.000.10 (1.693.004) ref ref (1.693.004) 43.000.10 dimensions in mm (inches) card body connection portion 10 mm (.394) area from connector side other area note: dimensions conform with jeida dram card ver.2.0.
26 MB98B7515/7516/7517/7518 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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